1. Field of the Invention
The present invention relates to semiconductor memory devices such as NAND cell, NOR cell, DINOR (Divided bit line NOR) cell and AND cell type EEPROMs, and more particularly to a semiconductor memory device in which a detection precision in a sense amplifier can be enhanced.
2. Description of the Related Art
The sense amplifier of a flash memory or the like semiconductor memory device decides the value of data basically by detecting the existence or nonexistence or the magnitude of a cell current which flows in accordance with the data of a memory cell. This sense amplifier is usually connected to bit lines (data lines) to which a large number of memory cells are connected, and the sensing schemes thereof are broadly classified into a voltage detection type and a current detection type.
With the voltage detection type sense amplifier, by way of example, the bit lines in states where they are separated from the memory cells are precharged to a predetermined voltage, the bit line is thereafter discharged by the selected memory cell, and the discharge state of the bit line is detected at a sense node joined to the bit line. In sensing the data, the bit line is separated from a current source load, and a bit-line voltage determined by the cell data is detected. This sense amplifier scheme is usually employed in a NAND type flash memory.
On the other hand, the current detection type sense amplifier senses the data by causing a read current to flow to the memory cell through the bit line. Also in this case, however, the bit-line voltage is determined by the cell data, and the data decision at the sense node joined to the bit line, finally detects the difference of the voltage based on the difference of the cell current.
In general, the voltage detection type sense amplifier and the current detection type sense amplifier have merits and demerits as stated below. The voltage detection type utilizes the charging and discharging of the bit lines, and hence, power consumption may be low. In a large-capacity memory of large bit-line capacitances, however, a long time is expended on the charging and discharging, and hence, high-speed sensing becomes difficult. Besides, the bit-line voltage is oscillated comparatively largely in accordance with the cell data, so that the noise between the adjacent bit lines becomes a problem.
On the other hand, the current detection type sense amplifier is capable of the high-speed sensing in such a way that the data is sensed while causing the read current to flow to the memory cell through the bit line. Besides, the amplitude of the bit-line voltage corresponding to the cell data can be suppressed to a small one by a clamping transistor (pre-sense amplifier) arranged between the bit line and the sense node, so that the noise between the bit lines is difficult to become problematic. In the current detection type sense amplifier, however, the power consumption enlarges more than in the voltage detection type sense amplifier to the extent that the data is sensed while the current is kept flowing.
In the NAND type flash memory of the enlarged capacity, the voltage detection type sense amplifier has heretofore been extensively employed. However, in a case where the capacity of the memory is enlarged more, how the high-speed sensing is performed with the power consumption suppressed becomes an important problem to-be-solved. Further, when the microfabrication and capacity enlargement of the memory are advanced, the dispersion of currents attributed to the resistance values of the bit lines becomes a problem.
More specifically, in the NAND type flash memory, a read voltage Vcg which turns ON or OFF the selected cell in accordance with the content of the data is applied to the control gate of the selected cell from which the data is read out, among the plurality of NAND-connected memory cells. Also, a path voltage Vread which turns ON the other unselected cells irrespective of the contents of the data is applied to the control gates of the unselected cells. Thus, the content of the data of the selected cell is decided, depending upon if the current flows to the bit line through the memory cells. The voltage of the bit line is determined by a voltage Vclamp which is fed to the gate of the bit-line clamping transistor interposed between the sense amplifier and the bit line, and a voltage (Vclamp−Vthn) (where “Vthn” indicates the threshold voltage of the clamping transistor) is charged to the bit line. Since each cell operates in a linear region, the cell current tends to depend upon the drain-source voltage Vds of the selected cell. The voltage of the drain side of the selected cell is determined by the voltage of the bit line, the resistance value of the bit line, and the resistance values of the unselected cells nearer to the bit line than the selected cell, within a memory cell array, while the voltage of the source side of the selected cell is determined by the float of a source line (SRC), and the resistance values of the unselected cells nearer to the source line SRC than the selected cell, within the memory cell array. In this regard, there has also been proposed a technique for decreasing the cell current in such a way that the path voltage Vread which is fed to the unselected cells between the selected cell and the source line is controlled in accordance with the number of the unselected cells.
When the microfabrication and capacity enlargement of the memory are further advanced in the future, it is expected that the resistance value of the bit line will increase more and more. When the resistance value of the bit line increases, a dispersion occurs in the voltage of the drain side of the selected cell between in a case where the memory cell nearer to the sense amplifier has been selected and in a case where the memory cell remoter from the sense amplifier has been selected, and the dispersion of the voltage incurs the dispersion of the cell current. That is, in the case where the selected cell is remoter from the sense amplifier, a voltage drop IR-DROP ascribable to the bit-line resistance appears, and the voltage Vds of the selected cell decreases. As a result, the cell current becomes small. In the worst case, there is the problem that the read data will be erroneously decided.